[ Pobierz całość w formacie PDF ]from the HC11.
Multiple Exception When several exceptions occur simultaneously, the highest level of
Events exception and arbitration will normally win. Also, a subsequent higher
level of exception can interrupt a lower level exception routine.
For example, assuming a level 3 exception is in progress when a level 4
exception occurs. The level 4 exception is not masked out and will cause
the system to stack the PC and CCR and then start executing the
level 4 exception routine. The exception mask is now set to 4 and so a
subsequent level 4 exception of any arbitration level cannot exception
until the exception mask has dropped below level 4 once more. This will
happen as the RTI of the first level 4 routine restores the CCR. At this
point, the pending level 4 exception immediately takes control and the
level 3 exception must wait a while longer before resuming its task.
There is a short (2 µs to 4 µs) delay from the interrupt event occurring
and the CPU fetching the vectors. During this time, other interrupts may
occur of the same or higher interrupt level. It is during this period that the
arbitration takes place.
See examples in Figure 11 where three types of events can occur.
AN461
68 MOTOROLA
Application Note
Exception Handling (Interrupts)
SAME INTERRUPT LEVEL 2 EXCEPTIONS OF THE SAME INTERRUPT LEVEL,
EVENT B AT LEAST 2 µs AFTER EVENT A
MAIN ROUTINE
MAIN ROUTINE
EXCEPTION A EXCEPTION B
HANDLER HANDLER
INTERRUPT A
(IVL = 4,
IARB = $7)
DELAY BEFORE EXCEPTION IS PROCESSED
INTERRUPT B
(IVL = 4,
ARBITRATION HAS NO EFFECT SINCE B OCCURS AFTER EVENT A VECTORS ARE FETCHED.
IARB = $9)
ARBITRATION AT WORK 2 EXCEPTIONS OF THE SAME INTERRUPT LEVEL,
EVENT B 0.5 µs AFTER EVENT A
MAIN ROUTINE MAIN ROUTINE
EXCEPTION B EXCEPTION A
HANDLER HANDLER
INTERRUPT A
(IVL = 4,
IARB = $7)
DELAY BEFORE EXCEPTION IS PROCESSED
INTERRUPT B
(IVL = 4,
ARBITRATION TAKES EFFECT SINCE VECTORS HAVE NOT YET BEEN FETCHED.
IARB = $9)
HIGHER INTERRUPT LEVEL OCCURS DURING EXCEPTION PROCESS
MAIN ROUTINE MAIN ROUTINE
EXCEPTION A EXCEPTION A
HANDLER HANDLER
INTERRUPT A
(IVL = 4,
IARB = $7)
EXCEPTION B
INTERRUPT B
EXCEPTION A IS INTERRUPTED AND EXCEPTION B
HANDLER
HANDLER RUNS. WHEN B IS COMPLETE, A WILL
(IVL = 5,
RESUME AND COMPLETE ITS TASK AND RETURN TO
THE MAIN ROUTINE.
IARB = $1)
Figure 11. Multiple Interrupts
AN461
MOTOROLA 69
Application Note
Prioritization Prioritizing exceptions is normally self evident from the system
specification, but when converting from HC11 code it is worth careful
Schemes
consideration where it is required on the HC16. The HC16 is much faster
than the HC11 and most HC11 interrupt routines will not account for the
possibility of being interrupted themselves, so leaving all routines at the
same level of interrupt will normally work perfectly.
The flexibility of the exception scheme may seem rather daunting, but
there are just a few key points to remember:
1. Simultaneous exceptions of the same interrupt level are arbitrated
on the basis of the IARB0 IARB3 bits in each of the module
control registers and so these must be unique.
2. An exception of the same level as the current exception mask
cannot be executed until the mask level reduces below that
pending exception level except for level 7 exceptions.
3. A higher level exception will interrupt a lower exception level
routine which must then wait until the exception mask has
returned to its level before continuing.
4. Level 7 exception is highest interrupt level and is a non-maskable
exception that can be interrupted by another level 7 exception.
5. An arbitration level of 0 will cause a spurious interrupt if any
interrupt occurs from that module.
Exception Routine An HC11 interrupt takes the same amount of time as the SWI instruction
to get into the interrupt routine (14 cycles) but the CPU16 exception must
Entry Latency
also clear the pipeline in addition to the operations common with the SWI
command and so the SWI command takes 16 cycles while the exception
takes 20 cycles (4 to reload 2 stages of the 3 stage pipeline).
If exception latencies are the reason for moving to the HC16, then
remember that the first line of the exception routine is guaranteed to
execute and could be a PSHM instruction. Making the first instruction a
NOP will reduce the time from a maximum of 18 cycles down to just
2 cycles in addition to the 20 cycles entry latency and 38 cycles for the
worst case instruction (EDIVS).
Included later are two exception routines that perform the same task,
one for the MC68HC11E9 and the other for the MC68HC16A1. The
similarity of the two routines is the most striking feature and emphasizes
the ease of code conversion. The differences are easily seen and will
invariably follow the same approach for any code conversion of an
exception routine from HC11 to HC16.
AN461
70 MOTOROLA
Application Note
Exception Handling (Interrupts)
The first difference is to remember to save the registers that are to be
used in the exception routine, but not necessarily those that are used for
global variables. As we can see, the accumulator D, IX, and K registers
are all changed within the routine, but the IZ register is used as a global
register and contains the base address of SRAM and so is not saved on
the stack. At the end of the routine, the registers are pulled back off the
stack with the same syntax as pushed onto the stack. The assembler
orders the registers to ensure that the unstacking order is reversed.
The XK register is different in the exception routine and so must be
initialized. This requires the use of accumulator B to make use of the
TBXK instruction.
In terms of execution speed, the HC16 manages to perform the entire
exception routine in 5.76 µs where the HC11 takes 35.5 µs. Also, the
worst case latency reduces to 2.3 µs from the HC11 s 20.5 µs.
Example 17. HC11 Timer Output Compare 2 Interrupt Routine
| |
| +----------+ |
| | | |
--- --------+ +--------| ----------------
A + B + C = 331 cycles
A = 331 cycles 258 ---> minimum low state (73 cycles)
B = PWM duty (256 2 cycles)
PWM frequency is 6.7 kHz (timer clock is same as bus clock)
Subroutine below takes 32 cycles (including interrupt latency)
until the output compare 1 is re-armed, plus an IDIV or FDIV
instruction may start executing with max 41 cycles left before done.
Thus min period for this must be 331 cycles since the rising
edge of the pwm must occur after the OC1 is re-armed.
Routine takes 71 bus cycles to complete (35.5 µs at 2 MHz)
with a worst case entry latency of 41 bus cycles (20.5 µs at 2 MHz)
; 14 interrupt latency
OC2_INT LDX TEMP_X ; 4
LDD TOC1+REGS ; 5
ADDD #PERIOD ; 4 256 (max PWM) + 2 + (max time) before
; switch to other table is complete
STD TOC1+REGS ; 5 write OC1
* The OC1 reg has been updated so this is the point at which the routine
* must get to before OC1 has to go high. Worst case is when OC2 has
* maximum delay (max duty cycle).
ADDD 2,X ; 6 get new compare for OC2 (added to OC1)
[ Pobierz całość w formacie PDF ]zanotowane.pldoc.pisz.plpdf.pisz.plkajaszek.htw.pl
